1. Field of the Invention
The present invention relates to a circuit device adapted to perform hierarchic row decoding in semiconductor memory devices.
The invention relates, particularly but not exclusively, to a device as above, which is adapted to perform hierarchic row decoding in non-volatile semiconductor memory devices comprising at least one array of memory cells with column-ordered sectors, wherein each sector has a respective local wordline group linked to a main wordline, the circuit device having a main wordline driver provided at each main wordline and a local decoder provided at each local wordline.
One of the most widely used memory array architectures in the manufacture of non-volatile memory devices integrated in a semiconductor, is a NOR type. In such architecture, memory cells that locate in the same row of the array have their gate terminals in common, and memory cells that locate in the same array column have their drain terminals in common. Moreover, all the cells in an array sector have their source terminals in common.
To individuate a particular memory location, it is sufficient that a given row and a given column be selected, for only one memory cell can situate at their intersection. In non-volatile memories, a cell comprises a floating gate transistor having, moreover, drain and source conduction terminals.
The solution proposed has a specific application to decode architectures of the hierarchic type and reference will be made to such architectures for convenience of illustration.
2. Description of the Related Art
A first known type of architecture for non-volatile memory arrays comprises row-ordered sectors and corresponding row decoders associated with each sector.
This architecture uses up much circuit space, since a decoder for each sector must be provided, as well as local column decoders, to avoid the xe2x80x9cdrain stressxe2x80x9d phenomenon.
It is important to further consider that the memory array rows are materialized by polysilicon stripes laid to interconnect all the gate terminals of cells in one row.
From an electrical standpoint, each polysilicon stripe may be regarded as a distributed RC network. For example, the time constant of an array row defined by the RC network is approximately 10 ns, even when the number of cells is relatively small, e.g., 1024.
The above time value represents the time required for an electric signal to propagate through an array row, and directly affects the memory access time, which is required to be the shortest possible, as is well known.
Owing to the high density of cell integration in the integrated memory circuit, the local bitlines and the main bitline are formed by a process that consists of depositing two different layers or metal levels; short-circuiting the polysilicon row and shortening the row charge time become impossible unless a third metal level is provided.
Another known technical solution provides for the non-volatile memory arrays to be column-ordered. In this case, the array rows are shared by all sectors, and the size of a sector is set by the number of columns.
With an architecture of that type, the parasitic capacitance of each bitline is kept quite low, this being of substantial benefit to the circuit portion that is to read the memory contents.
Also, row decoding can be shared by several sectors, with attendant savings of circuit space.
Where an array is fabricated using a technological process that provides for two metal levels, one level is utilized to form the bitlines and the other level utilized to short-circuit the row for lower parasitic resistance during the charging phase.
Although advantageous on many counts, this prior architecture also has a drawback in that, each time that a cell is addressed, all the cells in the same row are biased and subjected to xe2x80x9cgate stressxe2x80x9d.
Furthermore, the information stored in non-volatile memories of the flash EEPROM type must be erased in groups or packets of bits. Erasing is the single operation where the source terminal is biased, and since all the cells have this terminal in common, they must be erased simultaneously, even though they can be written and read independently.
More particularly, flash memories are erased by the sector, meaning that all the cells linked to the same source line are erased simultaneously.
A circuit device adapted to perform erasings by negative voltages in column-ordered memory arrays is disclosed in the Applicant""s Published European Patent Application No. 0 991 075. This device is also shown schematically in FIG. 1 in relation to a single array sector, generally designated 1.
It should be noted that the cells contained in the sectors of the non-volatile memory array associated with the device 1 are ordered into plural wordlines or local rows, designated LWL (Local Word Line). In parallel with each array row, a main row- or wordline is provided, which is designated MWL (Main Word Line) and extends through all the sectors that have main rows in common. Within each sector, the circuit device 1 is connected upstream of each local wordline LWL of the memory array.
The memory device is supplied a single supply voltage Vdd, in the range of 2.5 to 3.6 Volts, and is connected to a second reference voltage GND, e.g., a signal ground.
The device 1 comprises a plurality of local decoders 2 connected between each local wordline LWL and the main wordline MWL, to which said local lines are linked.
The device 1 further includes, provided at each main wordline MWL, a main wordline driver 3, which comprises basically a pair of MOS transistors mounted in a pull-up/pull-down configuration and connected between first TVGLOB and second TSRC bias terminals to correspondingly receive first VGLOB and second SRC bias signals.
Each local decoder 2 comprises a first transistor M1 of the PMOS type having one of its conduction terminals connected to the main wordline MWL and the other connected to the local wordline LWL.
The body terminal of transistor M1 receives the first bias signal VGLOB, its gate terminal receiving a first tripping signal PCH.
The gate terminals of all the transistors M1 of the local decoders 2 associated with the array rows in one sector are connected together and receive the same voltage signal.
The local decoder 2 further comprises a second transistor M2 of the NMOS type having one of its conduction terminals connected to the main wordline MWL and the other connected to the local wordline LWL.
The body terminal of transistor M2 receives the second bias signal SRC at a negative voltage (about xe2x88x928V) during the erase phase, and the transistor gate terminal receives a second tripping signal NCH. The value of the second bias signal SRC is 0V (GND) for the other operations.
The gate terminals of all the transistors M2 of the local decoders 2 associated with the array rows in one sector are connected together and receive the same voltage signal.
Advantageously, an NMOS transistor M3 is connected with its conduction terminals between the local wordline LWL and the second bias terminal TSRC, the latter receiving the second bias voltage SRC as a negative voltage during the erase phase, and the signal ground GND for the other operations.
The body terminal of transistor M3 is connected to the second bias terminal TSRC, its gate terminal receiving a signal DISCH.
The gate terminals of all the transistors M3 of the local decoders 2 associated with the array rows in one sector are connected together and receive the same voltage signal.
In essence, this circuit device performs a row decoding of the hierarchic type by virtue of an additional transistor M3 in the local decoders 2 having one conduction terminal connected to the local wordline and the other connected to a ground voltage reference.
The technological trend toward the use of devices with ever higher cuts and densities in the field of memory devices poses important design problems, which are well recognized and have power consumption in the various modes (read, program, erase, etc.) of the device operation as their major aspect.
It should be noted, however, that most of the above power consumption is attributable to the use of xe2x80x9cboostedxe2x80x9d voltage generators that comprise charge pump systems integrated to the device. These systems include, for example, the systems employed to generate the read voltage, of about 6V, to the cell gate, and to generate the program voltages, in the 1.5 to 9V range and xcx9c4V, to the cell gate and drain, respectively.
Power consumption is in such cases directly proportional to the capacitive loads switched in during the various modes of the device operation.
Furthermore, xe2x80x9cboostedxe2x80x9d voltage generators have limited efficiency, cannot supply large currents with the output voltage maintained at a desired value, and involve substantial area overhead.
Thus, it can be appreciated that a reduction in power consumption achieved by reducing the driven loads would be a design contribution of great interest on several counts.
In conventional devices, however, the read and program voltages, applied to terminal TVGLOB, will of necessity reach the gate terminal of a selected cell through a driver 3, which is connected to the main wordline MWL, for example as shown in FIG. 1 illustrating the hierarchic decoding circuit device just described.
Note should be taken, moreover, of that the read and program voltage generators are to drive, additionally to the load of the selected main wordline MWL, the capacitive load from the substrates of the pull-up transistors of all the drivers 3, which represents a much heavier contribution because there is just one supply terminal provided for the drivers 3 of the main wordline MWL (in the extreme, it might serve all the main wordline drivers throughout the device).
In addition, the capacitive contributions from the local decodes (specifically, the substrates of the P-channel transistors) should be taken into account.
Thus, the overall switched load at each voltage variation at terminal TVGLOB is a sizable amount. It will be appreciated that this situation results in a high expenditure of power during all the operations involving xe2x80x9cfastxe2x80x9d switching of terminal TVGLOB (such as the transition from program to verify, and vice versa, during the program phase).
In view of a current-sensing approach method providing for the cell to be suitably biased at its terminals (e.g., Vgate=6V, Vdrain≈1V, Vsource=0V), and for the sensed electrical quantityxe2x80x94a function of the programmed state of the cellxe2x80x94to be its drain current, whereas the voltage-sensing method provides for the cell to be suitably biased at its drain and source terminals (Vdrain≈1V, Vsource=0V) and for its drain current to be forced to a suitable value, the sensed electrical quantity as a function of the programmed state of the cell being therefore the voltage produced at the cell gate, it is to be emphasized that the aforementioned problems equally affect the current- and voltage-sensing approach methods.
In other words, with conventional hierarchic row decoding, the gate terminal of a selected cell can only be reached electrically by going through a main wordline driver, and this regardless of which sensing method is used.
It should be further noted that, in conventional hierarchic row-decoding devices, the function of selecting the cell gate terminal is not disjoined from the function of transferring read and program voltages. In particular, in such conventional devices, the main wordline is to select an addressed cell by carrying itself the analog read and program voltages to the gate terminal of the cell.
An embodiment of this invention provides a novel circuit device for hierarchic row decoding, whereby a substantial reduction can be achieved in the capacitive loads that the various circuit systems are to drive during the memory cell programming and reading.
The circuit device for hierarchic row decoding also makes the architecture more flexible, in the sense that appropriate design options (far less critical than those of conventional devices) effectively lessen the capacitive loads driven in the presence of increased device cut.
The circuit device avoids a double function for the main wordline by having it perform the single duty of controlling a suitable switch to enable transfer of the read/program voltage to a local decoder, and through the latter, to the gate terminal of a selected cell.
In other words, the function of transferring the read/program voltage is served by a dedicated path which is distinct from the cell selecting path, and which in no way involves the overall row decode, the main rows and their drivers.
The features and advantages of a device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.